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A Novel Ultra Low Power CMOS Radio for
Wireless Sensor Nodes (WiSeNode) Research
team Mohammed Ismail,
Prof, KTH/ICT/ECS; e-mail: ismail@imit.kth.se Ana Rusu, Dr, KTH/ICT/ECS ; e-mail: arusu@kth.se Chithrupa Ramesh,
Wireless Systems MS student. MS thesis title “Flexible Scenarios for Wireless Sensor Networks” Sandeep Srinivasan,
SoC MS student MS thesis title “Ultra low-power CMOS Radio for Wireless Sensor Networks” Introduction A wireless sensor
network [1] as is shown in Figure 1, consists of a large number of
self-organized sensor nodes randomly deployed either inside a phenomenon or
very close to it. Sensor nodes are able to carry out simple computations
locally and transmit only the required and partially processed data. The data
is ultimately sent to a sink node with access to satellite or the Internet
for monitoring or network control [2], [3]. This enables a wide range of
applications in areas such as health, military and security.
Fig. 1 Sensor nodes
scattered in a sensor field Realization of such networks requires wireless ad-hoc networking
techniques but with special protocols and algorithms designed to achieve
fault tolerance and deal with large number of nodes. More importantly the
special protocols provide means to deal with the limited power, computational
capacity and memory of sensor nodes. For example, multi-hop communication in
sensor networks would consume much less power than traditional single-hop
communication, as transmission power levels can be kept very low. Low power consumption is the most important constraint on sensor
nodes as they carry limited, mostly irreplaceable power sources. So while
traditional wireless networks (e.g., cellular, WLAN) aim to achieve high
quality of service (QoS) provisions, sensor networks protocols focus mainly
on power conservation. The tradeoff is to prolong network lifetime at the
expense of lower throughput and/or higher transmission delay. Background
and
Preliminary Results Our group at
LECS/IMIT/KTH has done some of the pioneering work in configurable multi-band
multi-standard CMOS radio transceiver designs targeting emerging convergent
wireless standards beyond 3G such as WCDMA, 802.11a,b,g WLANs and Bluetooth
[4]. We published extensively and wrote several monographs in this area. We
recently lead a team that developed one of the very first CMOS multi-standard
(802.11a,b,g) WLAN single chip radios having the smallest die size and
consuming the lowest current. In the fields of smart power CMOS radio design, optimization and
test, especially for short distance wireless applications, our group has
gained considerable expertise. The expertise gained spans all levels starting
with frequency planning, radio architectures and link budgets at the system
levels, down to sub-system and block level design and optimization. This also
includes innovative techniques to achieve programmable, digitally calibrated,
high performance that is robust with respect to random process variations and
operating conditions with the highest level of CMOS integration at the lowest
power consumption and smallest die size. We propose to exploit this wealth of knowledge in the development
of ultra lower small die size CMOS sensor nodes and build a sensor network
testbed for future exploration of sensor network design and applications as
well as for student training in this rapidly growing area. Project
Objectives and Goals Our focus in this
project will be on design and verification of ultra-low power RFIC and
mixed-signal CMOS technologies for a sensor node radio transceiver. We will
explore implementation challenges and we will propose CMOS design techniques
leading to ultra low power System-on-Chip (SoC) solutions for sensor nodes
suited for implementation in nanometer (95 or 65 nanometer feature size) CMOS
technologies. Our long term goal is to use the results of this work and of
other funded work such as RaMSiS SSF program to build a sensor network test
bed (WISENET), also in collaboration with Wireless@KTH and with other
entities within and outside KTH. The testbed will have a node density of 32
nodes in a 5 meter by 5 meter region. It will be a great tool and will be
made available for use by others within and outside KTH. Project
Description The block diagram
for a core of a sensor node is shown in Figure 2. The sensing unit is
composed of a sensor and an analog-to-digital (A/D) converter, which converts
the sensed phenomenon to a digital signal that is then fed to the processing
unit. A transceiver unit, the focus of this proposal, provides communication
between the node and the network. The processing unit manages the
communication protocols and processes the sensed signal. A power unit based, e.g., on fuel cell
technology or lithium coin cells [1], [5], is used to power up the different
units in the node. All these units need to fit together into a matchbox-sized
module. The form factor could even be smaller than a cubic centimeter. The
lifetime of a sensor network depends on the lifetime of the power resources
in the nodes.
Fig. 2 The block
diagram of a sensor node The power in a sensor node is consumed in three processes:
sensing, data communication with other nodes and local data processing.
Sensing power varies with applications or the complexity of detecting a
certain event. The processing unit is often based on a micro-controller. The transceiver unit may be passive or active optical device as
in smart dust motes [5] or radio frequency (RF). While RF technology is
associated with large path loss and may require complex modulation,
filtering, demodulation, etc., we propose to adopt RF for several reasons.
Sensor networks process packets at extremely low data rates that could be in
the range of a few Hz’s. Also they operate over very short distances allowing
flexible network frequency planning or frequency re-use. These will allow
implementation of an RF radio with very low clock-rate electronics. Current
commercial Radio designs such as Bluetooth or 802.11b SoCs are not adequately
efficient for sensor networks. There is certainly a need for designing ultra low power CMOS
transceivers suited for wireless sensor networks. The design process must
begin with an optimum system definition involving the frequency planning at
the network level, the air interface and the radio architecture. A design
based on a simple constant envelope modulation (such as on-off-keying aka
OOK) coupled with a near-zero-IF (IF frequency of 40 to 50 KHz) radio
architecture, as proposed in Fig.3 [6], should lead to a very low power
design in a small die size. The radio architecture will be based on time division duplex
(TDD). However, it will do away with an RF switch as we directly interconnect
the receiver and the transmitter at the front end. In the receive mode the
transmitter will be switched off and vice versa. It will also do away with a
power amplifier and a high gain low noise amplifier. The I-Q baseband chain
will be shared between the receiver and the transmitter. In the receive mode,
it will be inserted in the receive path, while in the transmit mode it will
be connected into the transmit path but in the opposite direction. This will
significantly reduce the die size of the radio. The baseband chain bandwidth
will be programmable digitally from a few Hz to a few MHz to handle a wide
range of sensor network applications. The Weak inversion CMOS regime of
operation will be exploited to bring current levels to the nano ampere range. |
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